The following piece of code shows a standard implementation of a synchronous process with an asynchronous reset. As soon as the reset signal rst is driven high, a reset is executed. If reset is low, the normal operation activates on every rising clock edge. The code snippet below shows a standard implementation of a synchronous process with a synchronous reset. The process is activated only on a rising clock edge, at which time either a reset or the normal operation is executed.
These ways of coding resets in VHDL are straightforward and efficient for simulation. Sigasi Studio can generate the code template for processes with synchronous or asynchronous reset. Further information on the Content Assist and Auto-complete can be found in the manual.
An alternative way of coding a synchronous reset is shown below. At the clock edge, the normal operation executes. If reset is active, the result of the normal operation is overridden by the reset action.
Unary reduction operator is present. It is more difficult to learn. It is easy to learn. Why VHDL? It provides a flexible design language. It allows better design management. It allows detailed implementations. It supports a multi-level abstraction. It provides tight coupling to lower levels of design.
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If you are a student, it's for free. Otherwise a license costs just about 30EUR. If you know and like Visual Studio, you will like this plugin! It's also quite sophisticated, as it supports renaming, finding references, goto definition, code completion, etc. Most free editors I tried before were missing those features. Sign up to join this community. Because Sigasi Studio understands your code while you type, it can help you to be more productive, produce higher quality code and excel in your work.
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